This invention pertains, in general, to semiconductor processing and, more specifically, to forming an integrated circuit device with a contact hole.
Interconnect technology is a factor in the ability to reduce the area of integrated circuit devices. Multi-level metallization layouts have assisted dimension shrinkage by having multiple metal lines share the same area of the device. In a multi-level metallization layout, a dielectric layer, termed an interlevel dielectric layer (ILD) or a pre-metal dielectric (PMD) layer, is formed between the first metal layer and the transistors. Typically, the dielectric layer is formed to isolate the metal layer from the transistors. To electrically connect the underlying gate of the transistors or the substrate (i.e. the source or drain region) to the first metal line, a contact hole is etched within the ILD layer and filled with a conductive material to form a contact plug. Typically, a contact hole is formed between two transistors. These contact holes are desirably small so the transistors may be close together but must also be reliable. There, thus, is a need for contacts that are reliable and allow for transistors to be close together.